Flash memory devices have been recognized as an attractive data storage option for mobile computers and smartphone devices because of their small size, light-weight, shock resistance, fast access speed, and low power consumption. It is anticipated that with further advances in flash memory technology, its popularity may rival or even outpace hard disks. However, due to the different construction and organization of flash memory as compared with a hard disk device, a special functionality commonly called Flash Translation Layer (FTL) is needed to manage the read and write operations of the flash memory to map the logical address to the physical address.
The host computer is accustomed to interfacing with a hard disk which is a block-based device that can be presented as a linear logically numbered set of sectors, and thus issues read and write commands specifying a logical sector address. On the other hand, flash memory devices are constructed of planes, blocks, and pages. Therefore, the Flash Translation Layer is operable to translate a sector access into a page or block access. During the address translation, the Flash Translation Layer typically looks up a address-mapping table. When performing an overwrite operation, the Flash Translation Layer may redirect the write operation to a physical address of an empty location that has been previously erased to improve speed performance, and later changes the next write address information in the mapping table.
One major consideration for the Flash Translation Layer software is memory access efficiency. Because flash memory has an erase-before-write requirement, and the unit size of memory to be erased is larger than the write unit size, performance degradation can be significant. A second major consideration for the Flash Translation Layer is the size of RAM (Random Access Memory) required to maintain its mapping tables and free memory space information. The flash memory device can endure only a fixed number of writes to a memory element before it loses the ability to retain information. The flash memory device control mechanism thus also manages wear-leveling, which uses extra writes and garbage collection algorithms to control and even out the number of writes on the memory elements. The total cost for the flash memory device is tied to its RAM requirements.